Hi all- Radek needs the normal ip address for the perfSonars. However, for the pings to work across a circuit... We do not have a predictable means of allocating IP subnets to VLANs that will work in all cases - particularly if there is a VLAN translation that occurs along the path. Since few of our GOLEs can actually do VLAN translation, and those that do will [hopefully] only do so when the primary vlan blocks, then we can assume that most provisioning will use the same VLAN end to end. I suggest we configure this for now and hope for the best... Remember, we are demonstrating the NSI protocol's ability to provision the connection end to end - not whether we can do automated IP configuration. We'll want to do better, but if the end systems can't ping for this reason, it does not mean the circuit is broken... Therefore, as we did for prior demos, each perfSonar should have a subnet mapped to each of the four VLANs: 10.250.xx.yy where XX is the last two digits of the VLAN (ex: for vlan 1780, map IPsubnet 10.250.80.00/24 to that vlan.) and where yy is the allocated hostid for each GOLE - NetherLight being .1, StarLight being .2, etc For example: NetherLight would configure ip address 10.250.80.1/24 on vlan subinterface 1780, and ipaddr 10.250.81.1/24 on vlan subinterface 1781, etc. The current allocations of host ID are listed below: NetherLight 10.250.xx.1 StarLight 10.250.xx.2 MANLAN 10.250.xx.3 CzechLight 10.250.xx.4 NorduNet 10.250.xx.5 CERN 10.250.xx.6 UvA 10.250.xx.7 PSNC 10.250.xx.8 JGN2 10.250.xx.9 AIST 10.250.xx.10 KDDI-Labs 10.250.xx.11 Caltech 10.250.xx.12 Univ of Essex 10.250.xx.13 i2CAT 10.250.xx.14 CESnet 10.250.xx.15 GEANT 10.250.xx.16 KrLight 10.250.xx.17 Hope this helps Jerry On 10/24/11 12:02 PM, Radek Krzywania wrote:
Hi all, I need your quick help with the FIA demo. It seems that everything is down, and we will not show NSI glory at all. I would like to ask all NSI domains to put their agents up and ready, and use newer version of NSI protocol if possible. I would also like to know all IP addresses of the servers attached to the end of circuits. Currently I have neither control plane nor dataplane ready. Could you please help with sorting this out. The FIA is already in progress and I was hoping to have the demo working by today morning.
Best regards Radek
________________________________________________________________________ Radoslaw Krzywania Network Research and Development Poznan Supercomputing and radek.krzywania@man.poznan.pl Networking Center +48 61 850 25 26 http://www.man.poznan.pl ________________________________________________________________________